1. Field of the Invention
The present invention is generally directed to the field of semiconductor processing, and, more particularly, to a semiconductor device with a gate dielectric having a width less than the width of the gate conductor, and method of making same.
2. Description of the Related Art
There is a constant drive within the semiconductor industry to increase the operating speed of integrated circuit devices, e.g., microprocessors, memory devices, etc. This drive is fueled by consumer demands for computers and electronic devices that operate at increasingly greater speeds. The speed at which integrated circuit devices, e.g., transistors, operate may be determined, in part, by the channel length of the transistor device. All other things being equal, the smaller the channel length of the transistor, the faster the transistor will operate. Thus, there is a constant drive to reduce the channel length on transistors to increase the overall speed of the transistor, as well as integrated circuit devices incorporating such transistors.
The ability to reduce the channel length, or feature size, of modem transistors is presently limited by modem photolithography equipment and techniques. Traditionally, components of a transistor, such as the gate conductor and gate dielectric, are made by forming the appropriate process layers above the surface of a semiconducting substrate, forming a layer of photoresist above the uppermost layer, developing and patterning the layer of photoresist to define a mask, and removing the portion of the process layer(s) that extend beyond the mask through one or more etching steps.
Using the traditional photolithography techniques described above, the feature size, e.g., the width of the gate conductor and gate dielectric, are directly formed in the layer of photoresist, or other similar masking layer, above the semiconducting substrate. In order to achieve further reduction in the feature size of transistors, e.g., the channel length, it is necessary to develop an alternative method that will allow formation of transistors with feature sizes smaller than that achievable with current photolithography techniques.
The present invention is directed to a semiconductor device that minimizes or reduces some or all of the aforementioned problems and a method of making same.